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Producing Microroughened Surface

IP.com Disclosure Number: IPCOM000091085D
Original Publication Date: 1969-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Cutillo, JG: AUTHOR [+2]

Abstract

In producing microroughened surfaces on printed circuit substrates, the conductors are covered with a removable protective coating to prevent application of insulative roughening resin. In A, substrate 1 is an insulative material to be roughened on its upper surface 2 for improving the adhesion of electrolessly plated metal. Conductive copper pin 3 extends to surface 2 for electrical connection with the plated metal. Removable protective coating 4 is formed on pin 3 by a method, for example, by immersing substrate 1 in sodium polysulfide to form a layer of cupric sulfide. Thin layer 5 of epoxy resin is applied over the entire upper surface of substrate 1 and coating 4 and cured with particulate matter, such as calcium carbonate particles 6 embedded in the epoxy as at B.

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Producing Microroughened Surface

In producing microroughened surfaces on printed circuit substrates, the conductors are covered with a removable protective coating to prevent application of insulative roughening resin. In A, substrate 1 is an insulative material to be roughened on its upper surface 2 for improving the adhesion of electrolessly plated metal. Conductive copper pin 3 extends to surface 2 for electrical connection with the plated metal. Removable protective coating 4 is formed on pin 3 by a method, for example, by immersing substrate 1 in sodium polysulfide to form a layer of cupric sulfide. Thin layer 5 of epoxy resin is applied over the entire upper surface of substrate 1 and coating 4 and cured with particulate matter, such as calcium carbonate particles 6 embedded in the epoxy as at B. After curing, the carbonate particles are leached out with acid, as at C, leaving voids 7. Then cupric sulfide layer 4 is removed by agitated immersion in potassium cyanide. The cyanide attacks the sulfide through voids 7 and releases the covering layer of resin on pin 3. Substrate 1 is then electrolessly and electrolytically plated at 8 over its surface with the result that pin 2 forms a good interconnection with the plating as in D.

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