Browse Prior Art Database

Generalized Circuit Chip

IP.com Disclosure Number: IPCOM000091097D
Original Publication Date: 1969-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Bonald, GM: AUTHOR [+2]

Abstract

Transistors T1 and T2, associated clamp circuits T3, T4 and T5 T6 and emitter-followers T8 and T9 are symmetrical with respect to points 1 and 1. With this arrangement, it is possible to interchange input A and reference voltage V REF with respect to terminals 1 and 8 and thus interchange the voltage levels appearing at the output terminal U. Transistors T10, T11 and T14, T15 provide gates for logic functions. To implement the gated coincidence logic function, input signals A and C are applied to terminals 1 and 3 respectively. V REF is applied to terminals 8 and 4. A common gating signal is applied to terminals E and P. The output signal is U = A C F + A C F = F (A Theta C).

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Generalized Circuit Chip

Transistors T1 and T2, associated clamp circuits T3, T4 and T5 T6 and emitter-followers T8 and T9 are symmetrical with respect to points 1 and 1. With this arrangement, it is possible to interchange input A and reference voltage V REF with respect to terminals 1 and 8 and thus interchange the voltage levels appearing at the output terminal U. Transistors T10, T11 and T14, T15 provide gates for logic functions. To implement the gated coincidence logic function, input signals A and C are applied to terminals 1 and 3 respectively. V REF is applied to terminals 8 and 4. A common gating signal is applied to terminals E and P. The output signal is U = A C F + A C F = F (A Theta C).

The gated Exclusive-Or circuit function is obtained by interchanging input A with V REF on terminals 1 and 8. This causes the output signal to be U = A C F + A C F = F (A theta C).

If separate gates are applied on terminals F and F, selective coincidence and Exclusive-Or logic function are provided. For the selective coincidence function, input A and V REF are applied to terminals 1 and 8 respectively. The output is U = A C E + A C F where E and F are separate gates. The selective Exclusive-0r function is obtained by applying input A and V REF to terminals 8 and 1 respectively. The output U = A C E + A C F.

Additional logic functions can be realized by incorporating additional inputs or gates or both and by defining additional points of symmetry.

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