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Sense Amplifier

IP.com Disclosure Number: IPCOM000091122D
Original Publication Date: 1969-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Strickland, SA: AUTHOR

Abstract

The circuit utilizes a periodic input signal generated by an emitter or similar device. The circuit provides output signals corresponding to the emitter signal and a gate signal which remains at an up level for the duration of a series of emitter pulses.

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Sense Amplifier

The circuit utilizes a periodic input signal generated by an emitter or similar device. The circuit provides output signals corresponding to the emitter signal and a gate signal which remains at an up level for the duration of a series of emitter pulses.

The input pulses from emitter 10 are coupled to input amplifier 12 which functions with pulse generating circuit 14 to provide output signals in synchronism with the emitter signals. Gate generating stage 11 generates a gating signal for the duration of a series of emitter pulses. In the steady state condition, transistors T16 and T18 are barely off. When the input at terminal 20 begins swinging positive, current is supplied to the base of T18 by T16. The voltage at the collector of T18 drops, turning off transistors T22 and T24. Transistor T26 is turned on, clamping the collector of transistor T18 one diode voltage drop above ground. During the steady state condition, transistor T28 is on and capacitor C30 is charged to a low voltage. When T22 and T24 are turned off, T28 remains on and C30 charges to a higher voltage. When the input at terminal 20 swings negative, the base drive to T16 decreases and the voltage at the collector of T18 starts to rise, thus turning T26 off and turning T22 and T24 on again.

When T22 and T24 turn back on, T28 is turned off until C30 discharges. Thus, a pulse is generated at output terminal 29 for each negative swing at terminal 20. The duration of this pulse is deter...