Browse Prior Art Database

Clocked Demand Response Data Transfer

IP.com Disclosure Number: IPCOM000091165D
Original Publication Date: 1969-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Hardin, DK: AUTHOR

Abstract

A high aggregate data transfer rate between a sending and receiving unit is accomplished by gating data at a constant clock rate for up to the storage capacity of the receiving unit and then reverting to a demand-response data transfer operation.

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Clocked Demand Response Data Transfer

A high aggregate data transfer rate between a sending and receiving unit is accomplished by gating data at a constant clock rate for up to the storage capacity of the receiving unit and then reverting to a demand-response data transfer operation.

The sending unit contains n counters equal in number to the number of receiving units associated with the sending unit. The capacity of each counter corresponds to the maximum storage capacity of the buffer in the corresponding receiving unit. Decoders are associated with each counter for sensing the count in the corresponding counter and producing a positive control signal whenever the maximum count is reached. Assume a data transfer is to be made from the sending unit to receiving unit 2 which exceeds the storage capacity of the buffer in the receiving unit. Initially, the count in counter 2 is zero and decoder 3 applies a negative signal which is inverted by inverter 4 to a positive signal to condition And 5.

When the sending unit is ready to transmit data via the simplex data bus, a pulse is applied to the advance 2 line and is passed via the conditioned And 5 to increment counter 2 and to signal receiving unit 2 to sample the data bus. This process is repeated with advance pulses being applied at a constant clock rate until counter 2 reaches its maximum count. This condition is sensed by decoder 3 to apply a signal via inverter 4 to block And 5 from responding to any further pulses on the advance 2 line. Thus, no further data can be gated to receiving unit 2 until counter 2 is decremented. Meanwhile, the sending unit can be gating data to other receiving units.

When receiving unit 2 transfers a unit of data onward from its buffer, it frees a storage position permitting a further data transfer from the sending unit. Thus, for each unit of data transferred from receiving unit 2, a pulse is applied to the corresponding RU2 Free line which is transmitted back to the sending unit to decrement the corresponding counter 2. Decoder 3 senses the fact that the counter is no longer at a maximum count and...