Browse Prior Art Database

Circuit to Eliminate Contact and Reject Noise

IP.com Disclosure Number: IPCOM000091203D
Original Publication Date: 1969-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 28K

Publishing Venue

IBM

Related People

Getzlaff, KJ: AUTHOR [+2]

Abstract

Drawing I shows a circuit for eliminating noise caused by contact bounce in switches. It is useful in environments in which the electrical signals from the switches are applied to extremely high-speed transistor switching circuits which respond to low-level, short-duration data and noise pulses.

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Circuit to Eliminate Contact and Reject Noise

Drawing I shows a circuit for eliminating noise caused by contact bounce in switches. It is useful in environments in which the electrical signals from the switches are applied to extremely high-speed transistor switching circuits which respond to low-level, short-duration data and noise pulses.

Switch signal A, also as in drawing B, is applied at a positive or negative level to Exclusive-Or 1, the output of which is applied to a single-shot 2 by way of a negative And 3. The other input to Exclusive-Or 1 is derived from the output G of bistable latch 5. The output of single-shot 2 is applied in true form B to negative And 4 of latch 5 and is also applied to And 4 in complement form C with a predetermined time delay caused by its transition through a plurality of inverters 6. Signal B is also applied to negative And 7.

This has its output F connected to an input of negative And 8 in latch 5. The latter produces a negative output signal G when all three inputs to And 4 or all three inputs to And 8 are negative. Signal A is applied in complement form to And 7 by way of inverter 9.

Drawing II shows the signal levels at various points in the circuit of drawing I. When Machine Reset goes positive, reset of latch 5 produces a positive level at
G. With G and A positive, the output of Exclusive-Or 1 is positive. When A goes negative upon actuation of the contacts, H then J go negative to fire S-S 2. B goes positive to inhibit setting of latch 5 at this time. C goes negative partially preparing And 4. When S-S 2 restores itself, the input conditions of 4 are satisfied as at E, causing the latch to be set and producing a negative output at
G. F and Machine Reset are negative at this time so that the latchback circuit from G to 8 causes latch 5 to be maintained in its set...