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Browse Prior Art Database

Series to Parallel A To D Converter

IP.com Disclosure Number: IPCOM000091259D
Original Publication Date: 1967-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Lynch, RJ: AUTHOR

Abstract

Converter 10 has analog-to-digital operational mode capabilities provided by the lower and upper circuits 11 and 12 respectively.

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Series to Parallel A To D Converter

Converter 10 has analog-to-digital operational mode capabilities provided by the lower and upper circuits 11 and 12 respectively.

Circuit 11 has n plural stages, each of which has a pair of complementary- type first and second transistors, e.g., T1 and T1', respectively, of the first stage. The first transistor T1...Tn of each stage is an emitter-follower and biases the base of the corresponding type transistor of the succeeding stage. The base of T1 is connected to terminal 13 and fed by signal V1in. The collector of each T1...Tn is coupled to the base of the other transistor T1'...Tn' of its corresponding stage. Overload diodes D1...Dn are provided to protect T1'...Tn' for those applications where a large number of stages is required. Each diode D1...Dn is connected between the base and the collector of the first and second transistors, respectively, of a particular stage for this purpose. The emitters of T1'...Tn' are commonly connected to terminal 14 to which is applied enabling or gating signal +V2in. The collectors of T1'...Tn' are commonly connected through their respective resistors R1...Rn to terminal 15. A negative bias supply -V3 is applied to terminal 15. Each of these collectors is also connected to one of output terminals X1...Xn.

To operate in an analog mode, T1...Tn and T1'...Tn' are initially biased in their off condition. V2in is at a predetermined constant positive level. Thus, prior to the application of V1in to the base of T1, each base voltage Vb1...Vbn of T1...Tn is essentially at ground during period t0 to t1, drawing B. Correspondingly, each collector voltage Vc1...Vcn of T1...Tn is at a positive level
Vx. Each collector voltage Vc1'...Vcn' of T1'...Tn' is substantially at the negative voltage level -V3.

At time t1, ramp voltage V1in, for example, is applied to the base of T1. V1in does not produce an immediate effect upon the circuit until time t2. At such time, threshold level Vt of T1 is reached by V1in and consequently T1 begins to conduct. When this occurs, Vc1 is clamped to ground. As a result, the base of T1' is placed above its threshold level Vt'. Consequently T1' begins to conduct causing its Vc1' to rise from -V3 to the +V2in level, thus generating an output at X1. Vc1 of T1 at time t2 commences to follow the input ramp V1in. When Vc1 reaches the threshold level Vt' of T1' at time t3, the latter is again cut off and Vc1' returns to the -V3 level.

At time t2, the emitter voltage of T1, which is also the input voltage Vb2 to the base of T2, commences to follow V1in. At time t3, it reaches t...