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Set Reset Latch

IP.com Disclosure Number: IPCOM000091262D
Original Publication Date: 1967-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Burke, RG: AUTHOR

Abstract

In this latch, transistor T1 and associated circuitry comprise a constant current source for transistors T2...T5. Normally T2 and T3 are nonconducting, maintaining the base of transistor T6 positive. With T6 positive resistor R1 provides biasing to the base of T5 to maintain T5 conducting. When T5 conducts, transistor T7 is biased down by the potential at the collectors of T4 and T5. With T6 conducting and T7 biased down, the output S is up and the output S is down.

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Set Reset Latch

In this latch, transistor T1 and associated circuitry comprise a constant current source for transistors T2...T5. Normally T2 and T3 are nonconducting, maintaining the base of transistor T6 positive. With T6 positive resistor R1 provides biasing to the base of T5 to maintain T5 conducting. When T5 conducts, transistor T7 is biased down by the potential at the collectors of T4 and T5. With T6 conducting and T7 biased down, the output S is up and the output S is down.

To change the state of the outputs, a positive pulse is applied to the Set terminal. This biases T2 conductive thus dropping the voltage on the base of T6. When T6 goes down, the potential across R2 drops, turning T5 off. With T5 off, the potential at the base of T7 rises. The rising of T7 causes the voltage across R2 to rise, thus biasing T3 conductive so as to maintain T6 down after the termination of the Set pulse. Now the states of the outputs are changed so that the output at S is low and the output at S is high.

To reset the latch, T4 which is normally nonconducting is turned on by a positive signal to the Reset input. This turns T7 off and reverses the described process to return the latch to its initial state.

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