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Nonsaturating Cascode Latch with Two Outputs

IP.com Disclosure Number: IPCOM000091295D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Sechler, RF: AUTHOR

Abstract

This cascode switch does not saturate. An inverted output is provided. Set and reset are performed by one input and low power is consumed. The features of the circuit are gained by commoning emitters of Tx and Ty at output f2. When gate input G is down, output f1 follows the data input D. That is, f1 is up when D is up and f1 is down when D is down. When gate input G rises, output f1 is latched at the level existing at the instant when G rises and remains latched until G goes down again. Then f1 again follows the data input D. When f1 is latched, it remains at the latched level independently of variations of input D.

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Nonsaturating Cascode Latch with Two Outputs

This cascode switch does not saturate. An inverted output is provided. Set and reset are performed by one input and low power is consumed. The features of the circuit are gained by commoning emitters of Tx and Ty at output f2. When gate input G is down, output f1 follows the data input D. That is, f1 is up when D is up and f1 is down when D is down. When gate input G rises, output f1 is latched at the level existing at the instant when G rises and remains latched until G goes down again. Then f1 again follows the data input D. When f1 is latched, it remains at the latched level independently of variations of input D.

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