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Thin Film Transistor Using Thermally Grown SiO(2)

IP.com Disclosure Number: IPCOM000091299D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Fowler, AB: AUTHOR

Abstract

Thin-film transistor 1 is fabricated by depositing a low-resistivity elongated silicon body 3 on insulating substrate 5, e.g., of sapphire, by evaporation, sputtering, or pyrolysis. Body 3 serves as the gate electrode. Insulating layer 7 is thermally grown over body 3 and, subsequently, InAs channel layer 9 is deposited at a high temperature to exhibit large grains so that high carrier mobility is obtained in layer 9. Metallic source and drain electrodes patterns 11 and 13 are deposited over layer 9. Bias voltage applied to body 3 is effective to modulate conduction between source and drain electrodes 11 and 13.

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Thin Film Transistor Using Thermally Grown SiO(2)

Thin-film transistor 1 is fabricated by depositing a low-resistivity elongated silicon body 3 on insulating substrate 5, e.g., of sapphire, by evaporation, sputtering, or pyrolysis. Body 3 serves as the gate electrode. Insulating layer 7 is thermally grown over body 3 and, subsequently, InAs channel layer 9 is deposited at a high temperature to exhibit large grains so that high carrier mobility is obtained in layer 9. Metallic source and drain electrodes patterns 11 and 13 are deposited over layer 9. Bias voltage applied to body 3 is effective to modulate conduction between source and drain electrodes 11 and 13.

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