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Browse Prior Art Database

Logic Pattern Recognition

IP.com Disclosure Number: IPCOM000091312D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Moffitt, GT: AUTHOR

Abstract

In a clock phasing signal of a number of identical bits, a certain number of errors, three in this instance, is acceptable to phase the clock. Any errors over that number is cause to reject the data line. To count the number of errors, the phasing signal is fed to detector 1 including Exclusive-Or components 2 and two input And's 3. A bit on an S line indicates two bit errors. Circuitry 4 adds the errors and, if the number exceeds three, an error signal is transmitted on line E. If the number does not exceed three, the error sum is placed on the C' and S' lines and again added in circuitry 5. Finally the total number of errors is added in circuitry 6. At any circuit, if the number exceeds three, an error signal is transmitted on line E.

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Logic Pattern Recognition

In a clock phasing signal of a number of identical bits, a certain number of errors, three in this instance, is acceptable to phase the clock. Any errors over that number is cause to reject the data line. To count the number of errors, the phasing signal is fed to detector 1 including Exclusive-Or components 2 and two input And's 3. A bit on an S line indicates two bit errors. Circuitry 4 adds the errors and, if the number exceeds three, an error signal is transmitted on line E. If the number does not exceed three, the error sum is placed on the C' and S' lines and again added in circuitry 5. Finally the total number of errors is added in circuitry 6. At any circuit, if the number exceeds three, an error signal is transmitted on line E.

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