Browse Prior Art Database

Controlling Dimensions in Fabricating Integrated Structures

IP.com Disclosure Number: IPCOM000091326D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Silvestri, VJ: AUTHOR [+2]

Abstract

The method uses on electrolytic technique which permits the attainment of high resolution needed in the device region of dielectrically isolated integrated circuits. The basic method comprises the steps of:

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Controlling Dimensions in Fabricating Integrated Structures

The method uses on electrolytic technique which permits the attainment of high resolution needed in the device region of dielectrically isolated integrated circuits. The basic method comprises the steps of:

1. Forming n/n+/n- epitaxial germanium layers on a p+ germanium substrate by a low temperature, 500 degrees C, vapor growth process. The n/n+/n- epitaxial layers are replaced by a p/p+/n- structure if the active devices require a p-type collector region.

2. Forming a layer of SiO(2) on the surface of the epitaxially deposited layers and depositing thereon a layer of polycrystalline germanium at low temperatures.

3. Entirely removing the original p+ region by a p-type selective (0.1 N Na OH) electrolytic etching process which stops automatically upon encountering the n-region. The n-region can be kept as thin as 1-2 microns. This minimizes the amount of semiconductor material which must be etched to provide device isolating and thus permits increased packing density. After removing the p+ region, mesas are formed in the epitaxial layers by conventional photolithographic and etching techniques.

4. Backfilling the regions between the mesas with semi-insulating GaAs.

5. Stripping the polycrystalline germanium layer. The insulated islands of germanium are available for the formation of active devices by diffusion techniques.

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