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Multilayer Printed Circuit Board Registration and Lamination

IP.com Disclosure Number: IPCOM000091356D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Peter, AE: AUTHOR [+2]

Abstract

Dimensional accuracy between patterns in multilayer circuitry is attained. This is effected by using a disposable mandrel or electroforming substrate provided with holes or targets for pins or microscopic registration. Sheet 1 of stainless steel containing locating holes or slots 2 has a deposit of copper 4 electroformed on it as shown at A. Another reusable sheet 5 of stainless steel at B has electro-formed on it a deposit 6 of copper having slightly greater area than that of deposit 4. In C and D, dielectric sheet 7 is placed between electroforms 4 and 6 after which heat and pressure are applied to bond that of deposit 4. In C and D, dielectric sheet 7 is placed between electroforms 4 and 6 after which heat and pressure are applied to bond the assembly.

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Multilayer Printed Circuit Board Registration and Lamination

Dimensional accuracy between patterns in multilayer circuitry is attained. This is effected by using a disposable mandrel or electroforming substrate provided with holes or targets for pins or microscopic registration. Sheet 1 of stainless steel containing locating holes or slots 2 has a deposit of copper 4 electroformed on it as shown at A. Another reusable sheet 5 of stainless steel at B has electro-formed on it a deposit 6 of copper having slightly greater area than that of deposit 4. In C and D, dielectric sheet 7 is placed between electroforms 4 and 6 after which heat and pressure are applied to bond that of deposit 4. In C and D, dielectric sheet 7 is placed between electroforms 4 and 6 after which heat and pressure are applied to bond the assembly. Sheet 5 is removed and the circuit pattern etched using holes 2 in sheet 1 for alignment. These steps are repeated to build up the multilayer circuit to the number of layers desired as shown at B. When the circuit build-up is complete, new registration holes 8 and 9 are added and the laminated package is parted from the sheet 1 by suitable methods as in F.

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