Browse Prior Art Database

General Purpose Hardware Monitor

IP.com Disclosure Number: IPCOM000091357D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Anderson, DW: AUTHOR [+4]

Abstract

A hybrid system of external and internal elements is shown in A for monitoring the durations of activities within various sections of a data processing system. The external elements comprise probe connections to appropriate signal points within the processor being monitored, and timing, gating and counting logic circuits for developing the desired information, in the form of digital counts, from the probe signals.

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General Purpose Hardware Monitor

A hybrid system of external and internal elements is shown in A for monitoring the durations of activities within various sections of a data processing system. The external elements comprise probe connections to appropriate signal points within the processor being monitored, and timing, gating and counting logic circuits for developing the desired information, in the form of digital counts, from the probe signals.

The internal elements comprise hardware and software, within the central processing unit CPU, of the system being monitored or of another system if one is available, which are adapted to cooperate with the external elements to induce CPU program interruptions. These interruptions enable the CPU to develop in main, core, storage overflow, i.e., extended, counts as extensions of the counts developed externally and also, at strategic times, to transfer the external counts into storage.

Economy is achieved by extensive use of existing communication and interruption facilities of the computer in the transfers of counts and overflow counts from external counters to computer core storage. For a description of a communication and interruption facility of a computer particularly adaptable to this purpose refer to IBM OEMI Manual Form A22-6845.

The functions monitored by the counters of this system, shown schematically at B, include Real Time, CPU WAIT, CPU Busy In Supervisory Mode, and Channels 1...3 Busy. There is a rotary switch for each counter, not shown, which selects the function to be monitored. Additional gating logic, not shown, can be provided for conditioning the inputs to the counters on combinations of activity conditions, e.g., Channel and CPU Busy simultaneously.

The CPU WAIT and Supervisory Mode conditions are derived from the Wait bit W and the Not Problem State bit P of the current CPU program status word, PSW bits 14 and 15 respectively. The channel activity information is derived similarly from existing lines in the channel. The Operational In line is latched to signal Channel Busy. The Service In line is latched to signal data transfer activity, the latter latch being reset by a Status In signal.

Each of counters C1...C9 is an eight-place binary device. The counter inputs are derived from a common 4 megacycle clock pulse source CP. A first four-to- one frequency divider and decoder reduces the time base output to 1 microsecond periodic pulses at four discrete phases P1...P4. The pulses at P4, together with the output of the Real Time counter C1 and its two-place extension C1A, are decoded to produce further frequency-divided and phase-displaced outputs P5...P9 of 64 microsecond and 1024 microsecond duration. The phased pulses of 1, 64, and 1024 microsecond duration are applied through the activity conditioned gates &'s to the activity time counters C1...C9.

As indicated at C, since the counters are pulsed at different times they can be advantageously implemented as binary regi...