Browse Prior Art Database

Data Channel Simulator for Analog To Digital Conversion

IP.com Disclosure Number: IPCOM000091378D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Taylor, WA: AUTHOR

Abstract

This recording system is for recording analog data in digital form. The system, drawing A, consists of an analog-to-digital converter ADC 11 and tape synchronizer 12 controlling tape drive 13. Interface 14 is provided between ADC 11 and synchronizer 12. Interface 14 in conjunction with synchronizer 12 provides the various commands and controls which ordinarily are supplied by central processing unit CPU. Synchronizer 12 is usually a slave unit, i.e., it is controlled by some other unit. However, in this system, synchronizer 12 supplies the timing and control signals for the operations of interface 14. The latter receives a 10-bit data value from ADC 11 and causes synchronizer 12 to write this data on tape as two 6-bit characters. Interface 14 supplies the necessary extra two bits.

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Data Channel Simulator for Analog To Digital Conversion

This recording system is for recording analog data in digital form. The system, drawing A, consists of an analog-to-digital converter ADC 11 and tape synchronizer 12 controlling tape drive 13. Interface 14 is provided between ADC 11 and synchronizer 12. Interface 14 in conjunction with synchronizer 12 provides the various commands and controls which ordinarily are supplied by central processing unit CPU. Synchronizer 12 is usually a slave unit, i.e., it is controlled by some other unit. However, in this system, synchronizer 12 supplies the timing and control signals for the operations of interface 14. The latter receives a 10-bit data value from ADC 11 and causes synchronizer 12 to write this data on tape as two 6-bit characters. Interface 14 supplies the necessary extra two bits. Interface 14 also provides for a two-character identification tag to be written at the beginning of each data record. Moreover, interface 14 simulates a CPU by generating all the necessary commands for both reading and writing, generates parity, and converts data read from the tape into its original analog form.

A detailed arrangement of the recording system is in B. ADC 11 is associated with a sample-and-hold amplifier SHA 15 which requires a sample pulse. This causes SHA 15 to track the input signal until a hold command is given. The hold pulse causes SHA 15 to hold its output at the value the analog input has when the command is given. A trigger pulse is utilized to cause ADC 11 to convert to digital form the voltage which appears at its input from SHA 15. Conversion is a serial process starting with the high-order bits and takes about 20 microseconds. The bits are not available to the rest of th...