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Synchronized Transmission Systems

IP.com Disclosure Number: IPCOM000091379D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Irro, F: AUTHOR [+2]

Abstract

In synchronous data transmission systems, clocks in the receiver and transmitter must be kept in synchronism. This is generally done by adjusting the receiver clock by the data transitions in the signal from the transmitter. Since a long string of 0's or 1's has no data transitions and might allow the receiver clock to lose synchronism, it is customary to insert at regular intervals special characters for sync purposes. This results in a decrease of transmission capability. In this system, the capability decrease is minimized by inserting the synchronizing characters only when they are needed to maintain synchronism. Data signals to be transmitted are received on line S and pass through Or VI and are gated by clock line TT into first register stage TA.

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Synchronized Transmission Systems

In synchronous data transmission systems, clocks in the receiver and transmitter must be kept in synchronism. This is generally done by adjusting the receiver clock by the data transitions in the signal from the transmitter. Since a long string of 0's or 1's has no data transitions and might allow the receiver clock to lose synchronism, it is customary to insert at regular intervals special characters for sync purposes. This results in a decrease of transmission capability. In this system, the capability decrease is minimized by inserting the synchronizing characters only when they are needed to maintain synchronism. Data signals to be transmitted are received on line S and pass through Or VI and are gated by clock line TT into first register stage TA. On the next clock pulse, the signal is gated from TA into second stage TB and the next signal passes into TA. And AO tests the two stored signals for a 00 condition while And Al tests for a 11 condition. If either condition is present, the output of the set And passes through Or V2 to a set line Z. If neither is present, Inverter I1 applies a voltage on reset line L.

The set signal on line Z is passed through And AS by enabling signal UT and the normally up WA signal to the first stage T1 of binary counter T1, T2, T4, and T8. In the meantime, the SREG line receives the signals to be transmitted and they are passed through And ANS to the transmission line TRSM by the signal WA. If,...