Browse Prior Art Database

Monolithic Chip Stacked Array

IP.com Disclosure Number: IPCOM000091390D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Brooks, GA: AUTHOR [+4]

Abstract

This stacked array of monolithic chips permits more dense circuitry with no increase in wiring.

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Monolithic Chip Stacked Array

This stacked array of monolithic chips permits more dense circuitry with no increase in wiring.

A first monolithic semiconductor chip device 11 is bonded, with its soft metal contacts 12 facing upward, to the surface of insulating substrate 13. Electrical contact is established to a preformed lead frame 14, soldered or welded between conductive pattern 15 formed on the surface of substrate 13 and the respective contacts 12 of chip 11. Frame 14 is formed by such techniques as stamping or etching from materials such as copper, beryllium, molybdenum, etc.

Finally, a second chip device 16 having soft metal contacts 17 is bonded directly to the same leads in frame 14. Encapsulation of frame 14 and chip devices, by molding, coating, potting and the like, to form a mechanically stable package eliminates the need for substrate 13.

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