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Error Correction without Speed Degradation

IP.com Disclosure Number: IPCOM000091407D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Conzola, JS: AUTHOR [+2]

Abstract

Data integrity is a primary requirement for high reliability computer operation. Various approaches are used to enhance data integrity in core storage. An example is a duplication of storage so that data is stored or read simultaneously from two storage units. Another example is the use of error correction codes. The former requires duplicating storage while the latter introduces a delay due to the encoding and decoding requirements.

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Error Correction without Speed Degradation

Data integrity is a primary requirement for high reliability computer operation. Various approaches are used to enhance data integrity in core storage. An example is a duplication of storage so that data is stored or read simultaneously from two storage units. Another example is the use of error correction codes. The former requires duplicating storage while the latter introduces a delay due to the encoding and decoding requirements.

This system incorporates the advantages of these two approaches. This is accomplished by the use of a small auxiliary storage unit to hold an error correction code word. This word can be substantially shorter than the original data word so the second storage is small. Further, the auxiliary storage unit cycle is offset from that of main storage to accommodate the delay required for encoding data. Thus there is no sacrifice of time due to encoding. The data generated by the read operation is checked with conventional parity techniques and the calculations are initiated. The code word is read from the auxiliary storage unit and the data is again checked. If the data is correct, nothing is done. If an error is detected, the correction code word is used to generate the corrected data. There is no delay unless an error is detected.

Data on line 1 is entered into main storage 2 at an address supplied on line 3. This phase of the operation proceeds in conventional fashion. The data on line 1 is als...