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Analog to Digital Converter

IP.com Disclosure Number: IPCOM000091417D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Croisier, A: AUTHOR

Abstract

The analog-to-digital converter uses an eleven-bit encoding circuit in which the first bit is a sign bit and the ten other bits are coding bits. The analog voltage is passed through a sample-hold circuit SH. For each output level of SH, the current through resistor Zs is added successively with the different combination of currents coming through weighting resistors Z1... Z10. The resulting current is fed to the input of discriminator Delta. When this resulting current is found null by Delta, the encoding is then achieved by writing a 1 for each resistor supplied with a current and a 0 for each resistor not supplied with a current. Each weighting resistor current is, therefore, to be controlled by a driver responsive to a sequencing logic and to the Delta output. Such a driver is shown on the drawing.

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Analog to Digital Converter

The analog-to-digital converter uses an eleven-bit encoding circuit in which the first bit is a sign bit and the ten other bits are coding bits. The analog voltage is passed through a sample-hold circuit SH. For each output level of SH, the current through resistor Zs is added successively with the different combination of currents coming through weighting resistors Z1... Z10. The resulting current is fed to the input of discriminator Delta. When this resulting current is found null by Delta, the encoding is then achieved by writing a 1 for each resistor supplied with a current and a 0 for each resistor not supplied with a current. Each weighting resistor current is, therefore, to be controlled by a driver responsive to a sequencing logic and to the Delta output. Such a driver is shown on the drawing.

Sign latch L is common to all stages of resistors. Its set input is fed by a signal from the sequencing logic while its reset input is controlled by the discriminator Delta Logic. When the input analog signal and, therefore, the output of SH is positive, there is no reset signal from Delta and the latch L output is high. When the analog signal is negative, Delta sends a reset signal to latch L and its output level is low. Thus, for each sample to be analyzed, latch L is set if this sample is positive and reset if the sample is negative.

A bit latch is further associated with each weighting resistor.

This latch is provided to determine whether or...