Browse Prior Art Database

PCM Terminal Buffer

IP.com Disclosure Number: IPCOM000091425D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Croisier, A: AUTHOR [+2]

Abstract

On PCM lines, data is transmitted at the 1,77 Mbit/s rate, at irregular intervals. One bit is sent with each downgoing transition of the Clock. Whatever be the direction of transmission, transmit or receive, the clock is always provided by the PCM carrier system. On the Serial Data Adapter SDA side, whose operating rate is 1 Mbit/s, the clock frequency of the PCM lines cannot be used accordingly. Therefore the SDA must be controlled by a separate 1 MHz clock. Buffers are required to interface the SDA with the PCM terminal.

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PCM Terminal Buffer

On PCM lines, data is transmitted at the 1,77 Mbit/s rate, at irregular intervals. One bit is sent with each downgoing transition of the Clock. Whatever be the direction of transmission, transmit or receive, the clock is always provided by the PCM carrier system. On the Serial Data Adapter SDA side, whose operating rate is 1 Mbit/s, the clock frequency of the PCM lines cannot be used accordingly. Therefore the SDA must be controlled by a separate 1 MHz clock. Buffers are required to interface the SDA with the PCM terminal.

Interfacing is possible when the mean rate of incoming data matches the mean rate of outcoming data. However, the clock frequency of the terminal can vary slightly independently of the MHz clock. In order to prevent the saturation of buffers resulting in transmission errors, due to the fact that the mean rates of incoming and outcoming data do no longer match exactly, a slightly higher frequency, e.g. 1.02 MHz clock frequency, is chosen.

The position of the buffers in the general system is shown in drawing 1. Buffers SB and RB are connected between the SDA and the PCM terminal. SDA is used for sending data to and for receiving them from the channel. The PCM terminal sends data to the PCM lines or receives them from these lines. Buffer SB receives data as well as the 1 MHz clock pulses. It transmits data to PCM terminal at the rate of this PCM terminal, i. e., 1,77 MHz, insofar as it is not full with data coming from the channel. Buffer RB receives data from terminal at the rate of PCM lines. It transmits data to Send/Receive-Switch-Over at the rate of 1 MHz and stops transmitting as soon as it is empty. The 1 MHz clock is gated by the buffers before sending to SDA.

In drawing 2, each buffer is provided with at least three 16-bit shift registers with provision for parallel input and output terminals as well as Reset Rs, Read Rd, and Shift S Terminals. Register 1 deserializes the data. When it is full, its contents are transferred in parallel from Register 2 and reserializes the data. The time...