Browse Prior Art Database

Maintenance of a System

IP.com Disclosure Number: IPCOM000091430D
Original Publication Date: 1968-Jan-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Weber, H: AUTHOR

Abstract

The device traces intermittent timing errors in the hardware I/O area. It consists of monitoring hardware continuously, storing I/O signals into a special store and freezing it when an error occurs.

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Maintenance of a System

The device traces intermittent timing errors in the hardware I/O area. It consists of monitoring hardware continuously, storing I/O signals into a special store and freezing it when an error occurs.

The device consists of a core storage with pertinent logic and is a part of a processor but works independently of it. The device monitors control signals, timing, etc., in any area of the input/output devices and their control logic. A basic timer in each I/O unit is required indicating every degree, 360 out of 360, or every point, 20 out of 20, of a machine cycle or equivalent. This timer advances a cycle counter and is used to sense a desired number of signals in intervals given by this strobe. A signal is stored as 1 for up or 0 for down level, respectively, in one of the core planes.

The cycle counter contents are stored together with the signal to indicate its location. The initial status of the signals is stored in one position of the core storage always at time 0. In the next following two positions, the cycle counter contents is stored zero at time 0. At subsequent cycle points information is stored only if at least one signal has changed. That is, if during cycle points 4, 5, and 6 no signal is changed, no information is stored. If a signal change occurs, the level of all signals is stored in one position as 0's or 1's respectively. The momentary cycle counter contents are stored in the next following two positions.

If at the end of a...