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Channel Delay Test Unit

IP.com Disclosure Number: IPCOM000091438D
Original Publication Date: 1968-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Keefner, JC: AUTHOR

Abstract

Testing of I/O devices that are connected to the central processor of a computer system via channels is effected by simulating the specified number of control units and the maximum allowable length of interconnecting cable.

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Channel Delay Test Unit

Testing of I/O devices that are connected to the central processor of a computer system via channels is effected by simulating the specified number of control units and the maximum allowable length of interconnecting cable.

Control unit selection is controlled by the Select-Out, Select-In and Hold-Out lines. The Select-Out and Select-In-lines form a loop from the channel through each control unit to the cable terminator block, Select-Out, again through each control unit back to the channel Select-In. The Hold-Out is a line from the channel to all attached control units and is used to enable the Select-Out signal. Hold-Out, when used, minimizes the propagation of the fall of Select-Out.

A Select-Out pulse delay representative of the accumulated worst case propagation delays is provided by an adjustable delay device indicated generally at 1. The latter includes a noninverting receiver 2 and driver 3 that are used to maintain the logical loading characteristics of the channel. A negative-going Hold-Out signal from the channel turns on single-shot 4. Inverter 5 in the line to single-shot 6 assures that it is not turned on. Single-shot 4 turns of f in 3.5 microseconds. Such action produces a negative-going pulse that sets trigger 7 on, resulting in a turnon of the Select-Out pulse at interface control unit 8. The channel under test turns of f the Hold-Out pulse to receiver 2. Inverter 5 then triggers single-shot 6 to provide a 3. 5 microsecond...