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Op Code Independent Computer

IP.com Disclosure Number: IPCOM000091456D
Original Publication Date: 1968-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 36K

Publishing Venue

IBM

Related People

Weiss, DH: AUTHOR [+3]

Abstract

Writable Control Stores WCS, sometimes referred to as Electronically Changeable Control Stores ECCS, permit an Operation Op Code Independent Computer arrangement. An Op code is an arbitrary assignment of a bit pattern to an instruction definition. In present computers an Op code is the first eight bits of an instruction word. The maximum number of codes is therefore limited to 256. Op code independence allows an unlimited number of codes.

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Op Code Independent Computer

Writable Control Stores WCS, sometimes referred to as Electronically Changeable Control Stores ECCS, permit an Operation Op Code Independent Computer arrangement. An Op code is an arbitrary assignment of a bit pattern to an instruction definition. In present computers an Op code is the first eight bits of an instruction word. The maximum number of codes is therefore limited to 256. Op code independence allows an unlimited number of codes.

In a computer whose controls are dictated by a Control Store, an instruction is a sequence of micro-orders in one or more micro-instructions. Hence, an unlimited number of instructions can be defined. In addition since computers have a defined Op code set, presently less than 256 codes are defined, the Op code independent computer can be defined with or without this set. The following describes a computer which includes a fixed Op code set. All those instructions which are additional comprise the Op Code Independent set. The fully Op Code Independent computer is obtainable by removing the fixed set.

First Op code hardware and the Load Control Store instruction LCS are described. For all those instructions defined with OP codes, the first micro-instruction of each instruction is in a fixed Read-only store ROS area. All the remaining Op codes have their first micro-instruction in a writable area. Each Op code in the writable area has associated with it a routine number which identifies the location of the first micro-instruction. The Op codes, routine numbers, and writable control store addresses are hardware fixed as part of the following computer arrangement. Operation Code Routine No. Hexadecimal Address 00 0 800

01 1 801

.. . ...

.. . ...

FF 100 864

The LCS instruction is comprised of an Op code and address B2, D2. The address formed from B2 plus D2 identifies a control word in Main Storage. The format for the control word is:

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Bits 0...15 form the Main Storage address of the first WCS word. Bits 16...19 provide indirect addressing for the WCS word. Bits 25...29 represent bits 1...5 of the WCS address, WCS starting address, where the micro-instructions are to be loaded. Bits 32...39 are a flag field. Bits 40...47 are the routine number and are the absolute address of the first cycle of the routine being entered. Bits 48...63 hold the count of the number of WCS words to be loaded with this instruction.

The first word loaded into the WCS, as taken from Main Storage location B2 + D2, is loaded at the fixed address specified by the routine number. Each WCS word has a next address field which specifies the location of the next WCS word. This next address field is modified when the WCS word is loaded into the WCS.

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Therefore, the WCS starting address, contained in control word bits 24...31, is added to bits 1...5 of the next address field of that first word. The second WCS word is loaded at the address specified by the WCS starting address. The...