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Combined ADC DAC

IP.com Disclosure Number: IPCOM000091460D
Original Publication Date: 1968-Feb-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Bares, WA: AUTHOR [+3]

Abstract

Feedback control loop stabilization is incorporated in this analog digital converting system. The feedback loop operates to control the frequency of pulse wave generator 12 such that n counts are made by counter 14 in the time that triangular wave generator 16 changes from one reference value to another. The two reference values are ground and a fixed reference voltage obtained from source 18. Counter 14 is stepped by pulses from generator 12. The nth count of counter 14 sends a pulse to phase detector or time discriminator 20. Pulses obtained from logic circuit 22 comprising voltage comparators 24 and 26 and latching circuit 28 are also applied to detector 20. Logic 22 is arranged to set or reset latch 28 so that it is up during the positive excursion of generator 16 and down during the negative excursion.

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Combined ADC DAC

Feedback control loop stabilization is incorporated in this analog digital converting system. The feedback loop operates to control the frequency of pulse wave generator 12 such that n counts are made by counter 14 in the time that triangular wave generator 16 changes from one reference value to another. The two reference values are ground and a fixed reference voltage obtained from source 18. Counter 14 is stepped by pulses from generator 12. The nth count of counter 14 sends a pulse to phase detector or time discriminator 20. Pulses obtained from logic circuit 22 comprising voltage comparators 24 and 26 and latching circuit 28 are also applied to detector 20. Logic 22 is arranged to set or reset latch 28 so that it is up during the positive excursion of generator 16 and down during the negative excursion. When latch 28 is up, counter 14 is arranged to count up. When latch 28 is down, counter 14 counts down.

Detector 20 is arranged, by a differentiating circuit for example, so that a pulse is generated at the input when latch 28 goes up and when it goes down. Detector 20 is further arranged so that no output is generated at this pulse time if a pulse arrives simultaneously from the nth count stage of counter 14. But otherwise an output flows from detector 20 to control voltage generator 32. If the input pulse is ahead of the nth count pulse, generator 32 serves to speed up generator 12. If the input pulse arrives after the nth count pulse, generator 12 is caused to slow down.

Because of this synchronization of...