Browse Prior Art Database

Clock

IP.com Disclosure Number: IPCOM000091495D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Griffiths, PJ: AUTHOR [+2]

Abstract

In this circuit, tapped delay line 2 and counter 3 cooperate to provide a variety of clock cycles. Latch 4, delay 5, and And 6 are connected to provide a pulse at the start end of line 2 when latch 4 is set in response to a start signal. As the pulse travels down line 4, Invertors 7...9 are actuated according to the location of their connection to line 2. These Invertors isolate line 2 from other circuits that are connected to receive the clock signals.

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Clock

In this circuit, tapped delay line 2 and counter 3 cooperate to provide a variety of clock cycles. Latch 4, delay 5, and And 6 are connected to provide a pulse at the start end of line 2 when latch 4 is set in response to a start signal. As the pulse travels down line 4, Invertors 7...9 are actuated according to the location of their connection to line 2. These Invertors isolate line 2 from other circuits that are connected to receive the clock signals.

And 12 and delay 13 are connected to transfer the pulse from the end of line 2 to the start of such line to begin another cycle.

Delay 13 is for fine tuning a recycling pulse with respect to the preceding pulse. The recycling continues so long as controlling input 14 is maintained at And 12. This input is controlled by counter 3 according to the number of times the pulse appears at the end of line 2.

Delay 15 couples the pulse at the output of Invertor 9 to counter 3. Delay 15 assures that counter 3 does not step to the last count before the full width of the pulse appears at the output of And 12. Count decoder 16 responds to the state of counter 3 to provide input 14 to And 12 while the count is below a preset value. Decoder 16 also provides signal 17 when the preset value is reached. And 18 is connected to receive signal 17 and the pulse at the output of Invertor 9 to reset latch 4 when the preset count is reached. The outputs of Invertor 7 and similar circuits are controlled according to the count to prov...