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High Speed Single Error Correcting and Double Error Detecting System

IP.com Disclosure Number: IPCOM000091498D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Kolankowsky, E: AUTHOR [+2]

Abstract

The drawing shows a memory with error correction. The memory stores words of 72 bits having 64 data bits and 8 error correction code ECC bits. The ECC bits provide single-error correction and double-error detection. In the central processing unit CPU associated with the memory, 72-bit words are handled as 8 bytes each having 8 data bits and 1 parity bit.

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High Speed Single Error Correcting and Double Error Detecting System

The drawing shows a memory with error correction. The memory stores words of 72 bits having 64 data bits and 8 error correction code ECC bits. The ECC bits provide single-error correction and double-error detection. In the central processing unit CPU associated with the memory, 72-bit words are handled as 8 bytes each having 8 data bits and 1 parity bit.

For a fetch operation, the addressed word is read from the memory and the 64 data bits and the 8 ECC bits are stored in the fetch register and in the store register. Parity generators 1 and 2 provide parity signals to a register checker which produces an uncorrectable error signal to the CPU. A parity generator responds to the 64 data bits and generates 8 parity bits. The parity bits are stored in a parity register and are available as parity check bits for the 8 bytes of data. ECC generator 2 generates 8 ECC bits from the 64 data bits. If there is no error, the generated ECC bits match the ECC bits stored in the ECC register. A comparator receives the output of the ECC generator 2 and the ECC register and produces a comparison, i.e., syndrome. Appropriate syndrome bits are decoded in a byte error decoder to identify an incorrect byte. The other syndrome bits are decoded in a bit error decoder to identify the bit position of the error. If a double error is detected, an uncorrectable error signal is sent to the CPU.

A data error locator responds to the byte and bit error decoders to correct an error in the data register. An ECC bit error locator responds to the byte and bit error decoders to correct an error in the ECC register. A parity bit error locator responds to the byte error decoder to change the parity register to reflect the change in parity of the byte that has been corrected. Changing the parity register directly in this wa...