Browse Prior Art Database

Mirror Drive System

IP.com Disclosure Number: IPCOM000091500D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Hoffman, W: AUTHOR

Abstract

The system is for addressing drive lines in a magnetic memory. Drive line 2 has one end connected directly to ground. The other end is connected to ground through terminating resistor 3. At the connection to resistor 3, line 2 is connected to the collector terminals of NPN transistor 4 and PNP transistor 5. Transistor 4 is turned on to drive line 2 in the opposite direction for a read operation. In the memory there is a large number of drive lines. Each drive line has an individual terminating resistor and pair of transistors that are similar to those shown.

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Mirror Drive System

The system is for addressing drive lines in a magnetic memory. Drive line 2 has one end connected directly to ground. The other end is connected to ground through terminating resistor 3. At the connection to resistor 3, line 2 is connected to the collector terminals of NPN transistor 4 and PNP transistor 5. Transistor 4 is turned on to drive line 2 in the opposite direction for a read operation. In the memory there is a large number of drive lines. Each drive line has an individual terminating resistor and pair of transistors that are similar to those shown.

Transistor 5 and similar transistors, not shown, are arranged in a matrix. The transistors of each row have their emitter terminals connected together. The transistors of each column have their base terminals connected together. For each row of transistors, there is an emitter driver as illustrated by driver 6. For each column of transistors, there is a base driver illustrated by driver 7. The base and emitter drivers are connected to a single read current source 9. The latter is turned on in response to a read timing signal to supply the appropriate current levels for operating the magnetic storage elements. For energizing line 2 for a read operation, address signals are applied to drivers 7 and 6. The read current source is then turned on to apply a current to the drivers.

Transistor 4 is connected with similar transistors in a matrix. Base driver 12 is connected to control the base of t...