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Browse Prior Art Database

Hybrid Multiplier for Implementing Dot Products

IP.com Disclosure Number: IPCOM000091502D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Nagy, C: AUTHOR [+2]

Abstract

This hybrid device provides rapid multiplication of pairs of numbers used for dot product, autocorrelation and cross-correlation operations in computing values in pattern recognition and signal processing. The scalar product of two vectors can be computed as the sum of n-squared binary scalar products where n is the number of bits required to specify each component of the vectors.

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Hybrid Multiplier for Implementing Dot Products

This hybrid device provides rapid multiplication of pairs of numbers used for dot product, autocorrelation and cross-correlation operations in computing values in pattern recognition and signal processing. The scalar product of two vectors can be computed as the sum of n-squared binary scalar products where n is the number of bits required to specify each component of the vectors.

To form a binary scalar product, two binary vectors are entered into m-bit registers 10 and 11, and corresponding bits are combined in And register 12. The output of each position in register 12 is a fixed level of current or voltage depending on the binary value in the position. The outputs of register 12 are summed in parallel by operational amplifier 13. High-speed, analog-to-digital converter 14 connects amplifier 13 to log to base 2, m-bit long register 15. The output of register 15 is added by adder 16 into accumulator register 17, which has 2n + 1 + log to base 2 of m positions.

The bits are prepared in correct standard form prior to storage in array 18. The latter acts as a buffer when the correlation of time sequences is desired in connection with shifting data into A or B.

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