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Browse Prior Art Database

Shift Register Associative Memory

IP.com Disclosure Number: IPCOM000091513D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Terman, LM: AUTHOR

Abstract

This uses shift registers to realize an associative memory. The memory has a plurality of shift register loops A...N. The number of shift register loops is equal to the number of bits in a memory word. Each loop of n-bits stores one bit from each of n words. The loops are synchronized so that bits of the same word arrive at the outputs of their respective loops simultaneously.

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Shift Register Associative Memory

This uses shift registers to realize an associative memory. The memory has a plurality of shift register loops A...N. The number of shift register loops is equal to the number of bits in a memory word. Each loop of n-bits stores one bit from each of n words. The loops are synchronized so that bits of the same word arrive at the outputs of their respective loops simultaneously.

To perform a compare, bits arriving at input-output gates are detected via interconnections 4 by compare circuits 5 and compared with the reference field inputs via interconnections 6 from a register not shown. An output from each circuit 5 can be provided based on a comparison or a noncomparison of a reference bit with an input bit. Assuming outputs are provided only when a comparison occurs, outputs from each circuit 5 are carried via interconnections 7 to And 8. The latter provides a signal only if a comparison is made between each of the reference bits and the input bits.

To load the memory, the input bits are fed in parallel from a word register, not shown, over interconnections 1 via gates 2 to the same bit position on each shift register A...N and are shifted around the loop by a shift control pulse applied to interconnections 3. Thus, an input word distributed on a bit per loop basis is shifted synchronously around loops A...N.

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