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Floating Point Guard Digit

IP.com Disclosure Number: IPCOM000091547D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Frye, HE: AUTHOR

Abstract

The arithmetic and logic section of a central processing unit has two 64-bit registers, Reg A and Reg B, for acting on operands of sixteen hexadecimal digits. Operand digits placed in Reg B can be shifted to the right and to the left. Reg A does not have any shift capability. Thus, in add, subtract, and compare floating point operations, the fraction that is to be shifted for alignment of the fractions is placed in Reg B.

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Floating Point Guard Digit

The arithmetic and logic section of a central processing unit has two 64-bit registers, Reg A and Reg B, for acting on operands of sixteen hexadecimal digits. Operand digits placed in Reg B can be shifted to the right and to the left. Reg A does not have any shift capability. Thus, in add, subtract, and compare floating point operations, the fraction that is to be shifted for alignment of the fractions is placed in Reg B.

A floating point operand has 64 bits. The high-order eight bits represent the characteristic. The remaining low-order bits represent the fraction. During floating point operations, the characteristics of the operands are handled in area 10, while the fractions are placed in the low-order ends of Regs A and B. In order to increase the accuracy or precision of the floating point operations, the last digit shifted out of Reg B is retained as a guard digit.

To implement the guard digit operation, Reg B is provided with wraparound circuit 12. Upon a shift-right operation, the low-order digit in bit positions 60...63 is transferred to bit positions 0...3, by circuit 12, to become the guard digit. On a shift-left operation, the guard digit is transferred, by circuit 12, from bit positions
0...3 to 60...63. Bit positions 4...7 are deconditioned to prevent propagation of any digit through them. These positions are set to all 1's or all 0's depending on whether a true add or a complement add is required.

Upon completion of a true add, the guard digit is uncha...