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Flagging General Register Usage in Supplemental Indexing Operations

IP.com Disclosure Number: IPCOM000091550D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Coombs, JM: AUTHOR

Abstract

General registers are used in one computing system to hold interchangeably index and base address values, used to compute effective storage addresses, and general information used in other computing operations. Occasionally index or base address values are used in computing operations not directly related to addressing of storage. As a result it can be expedient for a program to modify a general register value for one purpose, such as a supplemental indexing function augmenting a previously established function, but not for general computing functions. In such instances, flagging is useful to prevent mishandling of the register contents.

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Flagging General Register Usage in Supplemental Indexing Operations

General registers are used in one computing system to hold interchangeably index and base address values, used to compute effective storage addresses, and general information used in other computing operations. Occasionally index or base address values are used in computing operations not directly related to addressing of storage. As a result it can be expedient for a program to modify a general register value for one purpose, such as a supplemental indexing function augmenting a previously established function, but not for general computing functions. In such instances, flagging is useful to prevent mishandling of the register contents.

A flagged system in which such single purpose general register modifications can occur at random is shown in drawing A. It includes main store MS, sixteen general registers GR, other computing registers CR, instruction register IR, and arithmetic and logic unit ALU. The latter receives input information signals from the registers and supplies output result signals, via out bus AOB, to either MS or the registers. The bus connections to MS include addressing connections for applying effective address signals to MS and a data path for transferring storage data into and out of MS.

Instructions can have several different formats, one of which is shown. In this, the RX format, OP denotes the operations to be executed by the system. R,X, and B denote particular general registers GR used in the operation. Such an operation can involve a transfer of an operand from the GR specified by R to a location in MS. Such location has an effective address determined by adding together base address and index values obtained from the GR's specified by B and X, respectively, and a displacement value represented by D. The effect of this is shown in drawing B.

The sequence controls, which control the effective address computing function, are extended by SCE in drawing A to selectively condition and test flag registers FR which are associated on a one-to-one basis with registers GR. Each register FR contains two flag bits, ST to denote a supplemental Index Test and SM to denote a Supplemental Index Modification.

Upon first reference to any register GR as a source of base address B or index intelligence X, the extended controls SCE are adapted to turn on the ST bit in the FR corresp...