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Browse Prior Art Database

Ferrite Memory Arrays

IP.com Disclosure Number: IPCOM000091558D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Peter, AE: AUTHOR

Abstract

Simplification of the wiring of core planes in the Y and Z directions is attained by employing this printed circuit technique in their manufacture.

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Ferrite Memory Arrays

Simplification of the wiring of core planes in the Y and Z directions is attained by employing this printed circuit technique in their manufacture.

Stainless steel substrate 1 is plated with copper 2 to the thickness required for the lower circuitry plus the core as shown at A. Each toroidal core pattern 3 is then etched to the depth equal to the required core thickness. At B the etched toroids are next filled with an epoxy-ferrite or varnish-ferrite suspension 4 and the assembly is fired or sintered. All background copper about the outside diameter of the toroids is etched away to the depth of the cores and the assembly is filled with epoxy 5. The assembly is then cured and the top surface is ground prior to the application of a continuous layer of copper 6 of the required thickness for the upper circuitry.

The assembly is removed from substrate 1 and provides epoxy covered with upper and lower copper sheets joined together at the center of each toroid. Next, the circuit pattern shown at C is etched on each side of the assembly to provide the Y and Z leads. A core matrix can be assembled by stacking the assembly on locating pins and inserting an X wire through the center of the toroids.

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