Browse Prior Art Database

System for Bypassing Defective Memory Elements

IP.com Disclosure Number: IPCOM000091560D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Gillett, JB: AUTHOR

Abstract

This system is used in connection with main memory 1 having a large number of data memory elements, some of which are defective and incapable of storing bits correctly. Bits of information which would normally be stored in the defective elements of the main memory 1 are instead stored in supplementary memory 5.

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System for Bypassing Defective Memory Elements

This system is used in connection with main memory 1 having a large number of data memory elements, some of which are defective and incapable of storing bits correctly. Bits of information which would normally be stored in the defective elements of the main memory 1 are instead stored in supplementary memory 5.

A data word to be stored is entered into data register 4. The memory address of the word entered in register 4 is introduced to main memory register
2. One of the outputs of register 2 is connected to the input of associative memory 8. The latter has tag, flag, and address portions. For each main memory word location having a faulty bit position in just one section, a word containing tag, flag and address bits is recorded in the first free word location in the memory 8.

It is arranged that the tag bit portion of the word contains the address of the main memory word location and the flag bit portion defines the faulty bit positions in that main memory word location. The most significant bits of the address portion define the supplementary store segment associated with the same section of register 4 as the main memory word section containing the faulty bit positions. The remaining bits of the address portion contain the address of the first word location in the section of memory 5 which contains free bit positions corresponding to those defined by the flag portion. The flag portion of memory 8 selectively enable...