Browse Prior Art Database

System for Data Entry Display and Log Out

IP.com Disclosure Number: IPCOM000091565D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Allen, EL: AUTHOR [+2]

Abstract

This integrated apparatus is for manual entry, display, and log-out of data in a data processing system. In the apparatus, data is organized into bytes consisting of 8 bits where there are two 4-bit, hexadecimal characters per byte. A word consists of 4 bytes and a double word consists of 8 bytes.

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System for Data Entry Display and Log Out

This integrated apparatus is for manual entry, display, and log-out of data in a data processing system. In the apparatus, data is organized into bytes consisting of 8 bits where there are two 4-bit, hexadecimal characters per byte. A word consists of 4 bytes and a double word consists of 8 bytes.

Data is manually entered into the system by hexadecimal keyboard 2. The latter consists of 16 coded switches, each representing one of the 16 hexadecimal characters 0...9, A... F. Closing any one of the push button switches causes a 4-bit hexadecimal code to be read into the left or right side of data entry register DER. The latter is 1 byte wide so that it has space for two characters. Since keyboard 2 is coded, it only takes a single depression of a switch to enter one character into DER. From DER, bytes are gated either to the manual control data register MCDR or to the manual control address register MCAR. Bytes gated from DER to MCDR or MCAR pass through parity generator 4 which adds a correct parity bit to each byte. MCDR is a 64-bit, plus parity, register containing space for 8 bytes. MCAR is a 24-bit, plus parity, register containing space for 3 bytes.

The particular byte position within the respective registers to which a byte in DER is gated is under control of byte selector circuitry 5. When a double word of data is in MCDR, it can be gated to a storage unit, not shown, via 72-bit bus SDBI. Similarly, MCDR can be loaded by 72-bit bus SDBO from that storage unit. The address within the storage unit to which or from which double words are gated is under control of the address in MCAR. A 24-bit address in MCAR can be gated, for example, to a local store address register or to a main store ad address register, neither being shown. Status or register information to be displayed by the data processing syste...