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Ring Counter Check and Error Correction

IP.com Disclosure Number: IPCOM000091566D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Gerrand, F: AUTHOR

Abstract

The ring counter within the dashed line includes error detection and correction circuitry. The counter consists of the flip-flops F-F 1... F-F N. Only four stages are as an example. Under error-free conditions, only one of the N flip-flops has a 1 output at any given time so that all other flip-flops have 0. Each input step pulse, via input terminal 4, delivers a step signal through Or 1 causing a 1 to shift from one flip-flop to the next flip-flop. The error detection and correction circuitry, external to the dashed line detects, after a step pulse, the nonmovement of a 1, detects all 0's in the ring counter, and can be used to detect multiple 1's when more than one flip-flop has a 1. Additionally, error correction of a nonmovement error caused by a transient failure can be achieved.

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Ring Counter Check and Error Correction

The ring counter within the dashed line includes error detection and correction circuitry. The counter consists of the flip-flops F-F 1... F-F N. Only four stages are as an example. Under error-free conditions, only one of the N flip- flops has a 1 output at any given time so that all other flip-flops have 0. Each input step pulse, via input terminal 4, delivers a step signal through Or 1 causing a 1 to shift from one flip-flop to the next flip-flop. The error detection and correction circuitry, external to the dashed line detects, after a step pulse, the nonmovement of a 1, detects all 0's in the ring counter, and can be used to detect multiple 1's when more than one flip-flop has a 1. Additionally, error correction of a nonmovement error caused by a transient failure can be achieved.

Assume that the counter is set initially with F-F 1 having a 1.

A pulse at input terminal 4 cause an input, through Or 1 to the counter. The 1 output of F-F 1 along with the Or 1 step pulse satisfies the And 1, setting F-F 1 to 0 and F-F 2 to 1, thus transferring a 1 from F-F 1 to F-F 2. On the next pulse, F-F 1 is in the 0 state so that A1 is not satisfied, but A2 is satisfied by the Or 1 signal and the 1 output of F-F 2. Since A2 is satisfied on the second pulse, F-F 2 is set to 0 and F-F 3 is set to 1 via line 7. For each succeeding pulse, a 1 is transferred sequentially from flip-flop to flip-flop. If F-F 4 is the last stage of the counter, that is, N equals 4, then the output of A4 feeds the 1 input of F-F 1 at line 8 linking the last stage around to the first.

The error detection and correction circuitry consists of the And's A5...A8 controlled by inputs from the flip-flops of the counter and by inputs from the steering circuitry. The latter is located between terminal 4 and Or 1 and is operative to develop steering pulses to And's A5...A8. The steering circuitry consists of steering flip-flop F-F 5 which is alternately switched from 1 to 0 and 0 to 1 for each input pulse.

Assuming that F-F 5 is in an initial 0 condition and an input step pulse is applied to And's A12 and A13, only A13 corres...