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Inverse Mode Memory

IP.com Disclosure Number: IPCOM000091568D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Anderson, JL: AUTHOR [+2]

Abstract

The memory has an array of cores 2 which are arranged on row wires 5 and column wires 3. A third wire 4 is wound in two parts through the portion of the core plane that is shown. In a conventional memory organization, the row and column wires 5 and 3 carry half-select currents for addressing a particular core in the plane. Wire 4 carries an inhibit current during a write operation and carries a signal current produced by a core during a read operation. In this memory organization, wires 5 and wire 4 are connected to X and Y drivers to carry the half-select currents. Each wire 3 is arranged as a sense-inhibit wire.

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Inverse Mode Memory

The memory has an array of cores 2 which are arranged on row wires 5 and column wires 3. A third wire 4 is wound in two parts through the portion of the core plane that is shown. In a conventional memory organization, the row and column wires 5 and 3 carry half-select currents for addressing a particular core in the plane. Wire 4 carries an inhibit current during a write operation and carries a signal current produced by a core during a read operation. In this memory organization, wires 5 and wire 4 are connected to X and Y drivers to carry the half-select currents. Each wire 3 is arranged as a sense-inhibit wire.

For a read operation on core 2 and associated cores of the same word of data, drivers Y1 and X1 are turned on. Half-select currents from such drivers combine to provide a full-select current for core 2 and for the adjacent cores that are located on wires 4 and 5. The signal produced by core 2 is picked up on wire 3 and detected in a detector circuit for bit position 1. Signals from the other cores are similarly detected in associated detector circuits. Wires 3 are connected in balanced pairs on opposite sides of the memory plane. Each wire of a balanced pair receives equal noise voltages from the X and Y drivers. INVERSE MODE MEMORY - Continued These voltages are canceled in the detector circuits. The latter receive a signal on only one of the pair of lines because the half-select currents combine to provide a full-select current onl...