Browse Prior Art Database

Zero Delta Noise 3 D Memories

IP.com Disclosure Number: IPCOM000091569D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Anderson, JL: AUTHOR

Abstract

In a ferrite core memory, each unaddressed core that receives a half-select current level produces a small voltage, called delta noise. The latter is troublesome because e memories are usually arranged so that many cores receive a half-select current and contribute to the noise. In this memory, of the drawing, cores 2 are arrayed to receive half select currents on Y wire 3 and X wire 4. Z wire 5 carries the core signals during a read operation and carries an inhibit current from a Z driver 6 during a write operation. This memory is organized so that each wire 5 is coupled to a core that receives a full-select current level but is coupled to no cores that receive half select current levels. Thus this memory is free of delta noise.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Zero Delta Noise 3 D Memories

In a ferrite core memory, each unaddressed core that receives a half-select current level produces a small voltage, called delta noise. The latter is troublesome because e memories are usually arranged so that many cores receive a half-select current and contribute to the noise. In this memory, of the drawing, cores 2 are arrayed to receive half select currents on Y wire 3 and X wire 4. Z wire 5 carries the core signals during a read operation and carries an inhibit current from a Z driver 6 during a write operation. This memory is organized so that each wire 5 is coupled to a core that receives a full-select current level but is coupled to no cores that receive half select current levels. Thus this memory is free of delta noise.

Each Y wire extends through a row of cores. Each Z wire extends through a column of cores. Each X wire extends along a row through a number of cores that form a word of data and are to be addressed simultaneously. The X wire is then offset to another row. Thus, when drivers Y1 and X1 are turned on, full- select currents appear at the upper left-hand most group of cores. Only half- select currents appear elsewhere in the memory. Wire 5 which threads core 2 receives a signal produced by core 2 but it is not otherwise coupled to the two X and Y wires which carry half-select currents.

This arrangement is particularly adaptable to very large memories. The number of rows can equal the maximum number of cores that can be put on a single sense-inhibit wire 5. The number of cores in a row is a multiple of the number of cores selected for a word and can be as large as the number of cores that can be driven on the X or Y line. For example, there can be 2048 X wires, 2048 Y wires, and 2804 Z wires. The X and Y wires are coupled to 144 cores between offsets in the X wire. Thus there are 16 words of 144 bits each in each row of the memory. The memory...