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Monolithic Circuits With Isolated Faults

IP.com Disclosure Number: IPCOM000091570D
Original Publication Date: 1968-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR [+2]

Abstract

A monolithic memory has many identical memory cells formed in rows and columns on a chip of semiconductor material. During manufacturing tests, chips are found to have one or two bad cells. These chips can be interconnected to form a memory made up of selected good cells.

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Monolithic Circuits With Isolated Faults

A monolithic memory has many identical memory cells formed in rows and columns on a chip of semiconductor material. During manufacturing tests, chips are found to have one or two bad cells. These chips can be interconnected to form a memory made up of selected good cells.

The drawing shows a module having two chips 3 that are mounted on substrate 4 and connected to pins 5 by a pattern of conductors 6 formed on such substrate. A perfect chip may have, for example, 64 cells in substrate 4 and connected to pins 5 by a pattern of conductors 6 formed on such substrate. A perfect chip may have, for example, 64 cells in an 8 by 8 array. Two perfect modules contain 256 cells. One of the 16 X-dimension wires and one of 16 Y- dimension wires are energized to select one cell of each module for a memory operation. Additional modules are provided for each additional bit position of the memory word. The modules are mounted on a circuit card with other modules that contain selection and sensing circuits.

Chips that have one or two defective cells are organized as though they have 8 good cells in each Y-dimension but only 6 good cells in each X-dimension. Thus 16 X-wires and 12 Y-wires are connected to each pair of modules to address a selected cell and two Y-wires are left unused. Preferably, the chips are sorted into 4 groups having similarly located defects. Chips having a similar defect type are located at the corresponding position o...