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Binary To Decimal Conversion

IP.com Disclosure Number: IPCOM000091605D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Schmookler, MS: AUTHOR

Abstract

System CS converts binary fractions to decimal fractions by a high-speed method involving multiplying the binary fraction by 1000. The binary fraction is placed in Register 2. In each cycle of conversion, the binary fraction in Register 2 is multiplied by 1000 by feeding three arguments to the inputs of carry save adder CSA. One argument is obtained by shifting the fraction to the left corresponding to multiplying it by 1024. The second argument is shifted and complemented so as to multiply the fraction by -32. The last argument is shifted to correspond to multiplying the fraction by 8.

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Binary To Decimal Conversion

System CS converts binary fractions to decimal fractions by a high-speed method involving multiplying the binary fraction by 1000. The binary fraction is placed in Register 2. In each cycle of conversion, the binary fraction in Register 2 is multiplied by 1000 by feeding three arguments to the inputs of carry save adder CSA. One argument is obtained by shifting the fraction to the left corresponding to multiplying it by 1024. The second argument is shifted and complemented so as to multiply the fraction by -32. The last argument is shifted to correspond to multiplying the fraction by 8.

The outputs of CSA are connected to the inputs of parallel adder 3. The three arguments fed to CSA are added to produce a Sums argument and a Carries argument. Both are fed to the inputs of adder 3 which then provides a final sum output. The latter is fed back to Reg 2 to become the new fraction, and a 10-bit integer overflow that is fed to Register 4. Converter 5 receives the 10 bits from Reg 4 and converts them from radix 1000 to a radix 100 7-bit operand and to a 4-bit BCD digit representation of the hundred's digit. The digit and the operand are placed in Register 6. Converter 7 receives the 7-bit operand from Reg 6 and converts it from radix 100 to two BCD digits corresponding to the tens and units digits. Converter 7 transmits the hundreds digit and combines it with the tens and units digits. The three digits are then placed in the low-order end...