Browse Prior Art Database

I/O Interrupt Cancellation

IP.com Disclosure Number: IPCOM000091607D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Petersen, DA: AUTHOR [+3]

Abstract

In a class of I/O interruptions of the CPU instruction stream, such as Device End Type, CPU can be held up for a relatively long period of time during which the necessary status information is obtained from a given device. When CPU is ready to accept an I/O interrupt, the channel may not be immediately available to store the Channel Status Word CSW. This difficulty occurs because of the multiplexing capability of the Multiplexor Channel phi. While an interrupt is being requested by Channel phi, it must engage in byte or burst transfers with its I/O devices. If a byte transfer is occurring, the channel becomes available in a short period of time. If a burst transfer is occurring, the channel can be unavailable for storing the CSW for a long period of time.

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I/O Interrupt Cancellation

In a class of I/O interruptions of the CPU instruction stream, such as Device End Type, CPU can be held up for a relatively long period of time during which the necessary status information is obtained from a given device. When CPU is ready to accept an I/O interrupt, the channel may not be immediately available to store the Channel Status Word CSW. This difficulty occurs because of the multiplexing capability of the Multiplexor Channel phi. While an interrupt is being requested by Channel phi, it must engage in byte or burst transfers with its I/O devices. If a byte transfer is occurring, the channel becomes available in a short period of time. If a burst transfer is occurring, the channel can be unavailable for storing the CSW for a long period of time. A timeout is used to cancel the I/O interruption if CPU waits longer than a specified time for the channel to become available.

When the channel requests an interrupt, CPU performs whatever preliminary steps are required and proceeds to start the interrupt. This is effected by fetching the first half of the new I/O Program Status Word PSW and then transferring control to the channel. If the interrupt is other than a device end type, the interrupt operations proceed by storing the CSW and completing the interrupt as required.

If the interrupt is a device end type, CPU waits for the channel to become available for the interrupt. When the channel becomes available, the device is selected....