Browse Prior Art Database

Electron Beam Scan Memory

IP.com Disclosure Number: IPCOM000091610D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Karner, FA: AUTHOR

Abstract

Large-scale field-effect transistor FET matrices with electron beam scanning can be used for a memory device and scanning multiplexor.

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Electron Beam Scan Memory

Large-scale field-effect transistor FET matrices with electron beam scanning can be used for a memory device and scanning multiplexor.

A flat-faced cathode ray tube is arranged with matrix 1 of FET's on the beam side of the tube face. Drain electrodes 2 are connected in common to ground via resistor 9. Source target electrodes 3 are positioned in discrete locations. Metal plate 4, having thin insulation layer 5, is positioned outside the face of the CRT. A sufficient space, to accommodate chargeable memory card 6 of conductive foil material, is provided between plate 4 and the CRT face. Card 6 is perforated at locations 7 aligned with selected ones of electrodes 3. A cross-section of the tube face with an FET is shown at B.

Plate 4 is connected to a pulsed potential source 10 and serves as the gate for the FET's. In those locations 7 where card 6 is perforated opposite a selected electrode 3, the dielectric constant and gate potential are altered so that the FET does not conduct when its electrode 3 is struck by the electron beam. By sweeping electrodes 3 of the FET's with the electron beam, the voltage at output 8 from commonly connected electrodes 2 varies in accordance with the magnitude of the gate potential applied at the FET's concurrently with the beam. This can provide a read-only memory. A similar operation occurs when the FET matrix is rearranged by an interchange of position of the source and drain electrodes. A circuit for th...