Browse Prior Art Database

Stacked Storage Array Jumpering Technique

IP.com Disclosure Number: IPCOM000091617D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Betz, RJ: AUTHOR

Abstract

Core planes 10 can be joined by jumper wires 12 with a conductive exterior surface 16 and a nonconducting center 18. Slots 14 are punched in the edges of ceramic core planes 10 during their fabrication. When the core plane circuit pattern is metalized, slots 14 are also plated and then coated in a tin lead bath. When the completed core planes are stacked, jumpers 12 are inserted in slots 14. Jumpers 12 have conductive surfaces 16 plated or extruded over a nonconductive center 18. These conductive surfaces are bonded to the metalization pattern in slots 16. The metal used for conductive coating 16 is the same as the metal employed in the metalization patterns in slots 14. Conductive coating 16 is stripped away in certain places to isolate different connections made by the same jumper 12.

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Stacked Storage Array Jumpering Technique

Core planes 10 can be joined by jumper wires 12 with a conductive exterior surface 16 and a nonconducting center 18. Slots 14 are punched in the edges of ceramic core planes 10 during their fabrication. When the core plane circuit pattern is metalized, slots 14 are also plated and then coated in a tin lead bath. When the completed core planes are stacked, jumpers 12 are inserted in slots
14. Jumpers 12 have conductive surfaces 16 plated or extruded over a nonconductive center 18. These conductive surfaces are bonded to the metalization pattern in slots 16. The metal used for conductive coating 16 is the same as the metal employed in the metalization patterns in slots 14. Conductive coating 16 is stripped away in certain places to isolate different connections made by the same jumper 12.

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