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Browse Prior Art Database

High Speed Buffering

IP.com Disclosure Number: IPCOM000091632D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Blasbalg, HL: AUTHOR [+3]

Abstract

This system is for high-speed buffering. Multiplexing of digital inputs which are clocked from independent sources requires a retiming buffer in each channel to compensate for clock instabilities and offsets associated with each channel. Combining is done on a bit basis using a fixed interleaving pattern in the multiplex frame. Timing drawing 1 shows the relationship between the overall frame, subframe and combiner clock. A transmitter high-speed buffering method is shown in drawing 2. Channel interfaces 1...4 are connected to combining matrix 5. Channel interface 1 is typical and includes retiming logic 6, 4-bit counter 7, word detector 8, 10-bit counter 9, word detector 10, 10-bit synch code generator 11, control flip-flop 12, And's 13...15, Inverter 16, and Or 17, interconnected as shown.

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High Speed Buffering

This system is for high-speed buffering. Multiplexing of digital inputs which are clocked from independent sources requires a retiming buffer in each channel to compensate for clock instabilities and offsets associated with each channel. Combining is done on a bit basis using a fixed interleaving pattern in the multiplex frame. Timing drawing 1 shows the relationship between the overall frame, subframe and combiner clock. A transmitter high-speed buffering method is shown in drawing 2. Channel interfaces 1...4 are connected to combining matrix 5. Channel interface 1 is typical and includes retiming logic 6, 4-bit counter 7, word detector 8, 10-bit counter 9, word detector 10, 10-bit synch code generator 11, control flip-flop 12, And's 13...15, Inverter 16, and Or 17, interconnected as shown.

The complexity C, in bits, of logic 6, is a function of the bit rate R, the sum of clock instability and offset delta, and the time T over which bit integrity is to be maintained. That is, C = 2RT delta for a given channel. The value of T is chosen in the order of the frame duration which is normally in the order of milliseconds. Hence clock correction is made periodically and repeatedly at the frame rate. Bit integrity can be maintained indefinitely at a cost of only a few bits of retiming logic.

Assuming R is 10/6/ bits per second and delta is 5 parts in 10/3/, an overall frame duration of H/R = 1 millisecond is chosen, where R is channel bit rate and H is clock instability and offset constant reference. Within a frame there are H + delta = 1005 subframes, each comprising four bits, one per channel, as in drawing 1. Clock instability and offset is given as delta parts in H. Hen...