Browse Prior Art Database

Memory System having Distributed Data Parity and Bus

IP.com Disclosure Number: IPCOM000091633D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Palounek, LR: AUTHOR

Abstract

The drawings show a memory system and its organization of information. The memory system employs distributed data, parity and bus to achieve error detection and correction when used with a data processing system. The data is organized with eight bits Bktm per byte where m indicates a bit in the byte and is equal to 1...8 in each byte. Eight bytes are organized into a double word where each byte Bkl is indicated in a double word by l where l equals 1...8 for each double word Bk. Eight double words are organized into a group where each double word in the group is indicated by k where k equals 1...8.

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Memory System having Distributed Data Parity and Bus

The drawings show a memory system and its organization of information. The memory system employs distributed data, parity and bus to achieve error detection and correction when used with a data processing system. The data is organized with eight bits Bktm per byte where m indicates a bit in the byte and is equal to 1...8 in each byte. Eight bytes are organized into a double word where each byte Bkl is indicated in a double word by l where l equals 1...8 for each double word Bk. Eight double words are organized into a group where each double word in the group is indicated by k where k equals 1...8.

The memory system includes eight memory units or modules Mi, each having associated gates and part of distributed bus 5 which connect to the data processing system, not shown, through a storage control unit SCU SCU. Each byte of data is distributed over all eight storage units Mi with all Bkl1 in M1, all Bkl2 in M2 and so on. Each part of Bus 5 is eight data bits in width plus parity bits.

Thus one double word is read out per cycle or eight double words are read out per eight cycles depending upon the selected organization. In addition to the data bits Bklm, the memory system includes byte parity bits Pkl associated with the data bytes Bkl. Each of the sixty-four bits Pkl is stored in a memory unit Mi where i is defined as equal to the l of Pkl. For example, P11 and P81 are stored in M1. Similarly, P12 is stored in M2 and P88 is stored in M8. In accord with that manner of storage, the eight bits Pkl associated with a given double word Bk are distributed over the eight storage units M1...M8.

Each Pkl associated with a given word Bk has associated with it a parity on parity bit PPk. For example, the eight P1l byte parity bits are given correct parity by PP1. Similarly, the eight P8l bits have associated therewith the parity on parity bits PP8. The double parity bits PPk are distributed over the eight Mi where the i is defined equal to k. For example, PP1 is stored in M1 and PP8 is stored in M8. In addition to the byte parity Pkl and the word parity PPK, the memory system includes a triple parity bit, PPP, associated with the eight bits PPk. The triple parity bit PPP is redundantly stored in at least two memory units.

Each storage unit has associated with it a storage unit parity bit PMi. For example, all the bits Bkl1 in M1 are g...