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Adaptive Code Translation System

IP.com Disclosure Number: IPCOM000091636D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Clapper, GL: AUTHOR

Abstract

This system is capable of learning to translate any input code to any desired output code. For each input code combination, the trainer sets up the desired output code by actuating switches T1...TM. This adapts the internal memory so that whenever the input code is presented, the desired output code appear at the outputs 1...M. It is also possible to tag any undesired input combination with a special output code by this technique. In the example, an N-bit input code is shown where N is an even number. The number of bits in the output code M is flexible and can equal N and can be less than or greater than N.

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Adaptive Code Translation System

This system is capable of learning to translate any input code to any desired output code. For each input code combination, the trainer sets up the desired output code by actuating switches T1...TM. This adapts the internal memory so that whenever the input code is presented, the desired output code appear at the outputs 1...M. It is also possible to tag any undesired input combination with a special output code by this technique. In the example, an N-bit input code is shown where N is an even number. The number of bits in the output code M is flexible and can equal N and can be less than or greater than N.

The input code is divided into two groups. Each is expanded into 2/N/2/ combinations. These two groups are applied to the vertical and horizontal drive lines of a square combination matrix or decoder. The latter renders one and only one of its 2/N/ outputs active at any given time depending upon the input code applied to the register. The 2/n/ decoder outputs provide the inputs for the matrix of adaptive logic units. Each line from the decoder controls one row of adaptive logic units. The latter are grouped in vertical bands for training and output functions. There is one bank for each bit of the M bit output code.

In connection with the upper drawing, the number of bits N = 16. The four low-order bits and their complements are expanded to 16 output lines and are applied to the vertical axis of the decoder circuit. The four high-order bits and their complements are expanded in the high-order expansion circuit to 16 lines and applied to the horizontal axis of the decoder. Depending upon the code, one horizontal and one vertical line renders a single output line of the 256 available from the decoder circuit active. Switches T1...TM are set and the selected output line from the decoder, depending on the code inserted in the input register, conditions all adaptive logic units in that line as determined by the position of T1...Tm. If a 1 is desired at a position, the switch T associated with that position is set to apply a negative voltage to the adaptive logic units in its bank. If a 0 is desired in any given position, the associated switch T is positioned to apply a plus voltage. As illustrated, all of...