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Adder Circuit

IP.com Disclosure Number: IPCOM000091649D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Homan, ME: AUTHOR

Abstract

A full-adder circuit 10 can be implemented in one level of Nor-Or logic comprising eight individual circuits 12...19.

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Adder Circuit

A full-adder circuit 10 can be implemented in one level of Nor-Or logic comprising eight individual circuits 12...19.

Digit inputs from associated flip-flops, such as 20, are available and are labelled A and B. A carry input, from an associated adder circuit 22, is available and that carry input is labelled C. Combinations of A, B, C inputs are provided as indicated. For example, circuit 19 receives A, B, C, while circuit 15 receives A, B, C as inputs.

A signal on line 24 indicates that the sum of the digits and carry inputs provided to adder 10 is zero. A signal on line 26 indicates that the sum of the inputs is one. A signal on line 28 indicates that the sum of the inputs is two. A signal on line 30 indicates that the sum of the inputs is three, e.g., all three inputs are up.

A signal on lines 32 indicates no carry out of the adder circuit. A signal on lines 34 indicates a sum output of one. A signal on lines 36 indicates a sum output of zero. A signal on lines 38 indicates a carry output of one.

Input/output signals can be carried on a single line and intermediate signals bundled when adder circuits are assembled in groups, thus decreasing the number of either contact areas or conductive lines or both required on semiconductor circuitry implementing the adder function.

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