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Associative Memory Cell

IP.com Disclosure Number: IPCOM000091656D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Behnke, FA: AUTHOR

Abstract

This associative memory cell has only one bit line and one word line. This reduces the average number of input-output pins needed per cell when the circuit is constructed in monolithic technology. The circuit is implemented in insulated-gate field effect transistors. To write into the cell, switch SW1 must be switched to the voltage side while switches SW2 and SW3 remain as shown. This turns on transistor T4, transferring control of the write function to transistor T3. A positive-going pulse is now applied to word line 10. If a 1 is to be written into the cell, a positive-going pulse is also placed on bit line 12. If a 0 is to be written, no pulse is put on line 12 and it remains grounded through resistor R2.

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Associative Memory Cell

This associative memory cell has only one bit line and one word line. This reduces the average number of input-output pins needed per cell when the circuit is constructed in monolithic technology. The circuit is implemented in insulated- gate field effect transistors. To write into the cell, switch SW1 must be switched to the voltage side while switches SW2 and SW3 remain as shown. This turns on transistor T4, transferring control of the write function to transistor T3. A positive-going pulse is now applied to word line 10. If a 1 is to be written into the cell, a positive-going pulse is also placed on bit line 12. If a 0 is to be written, no pulse is put on line 12 and it remains grounded through resistor R2.

Assume that the cell has a 0 in it, that is, that point A is grounded through transistor T2. The positive-going pulse on line 10 conditions the gate of T3, turning it on. Now T2, T3, and T4 are all conducting and current flow is from ground through the three transistors to line 12. Since the impedances of T2 and T3, when conducting, are much less than the load imposed by transistor T10, point A begins to go positive toward voltage V(D). T1 begins to turn on, causing point B to go less positive thus turning off T2 until point A reaches voltage V(D) at which point a 1 is stored and the circuit stabilizes. To write a 0 in the cell, only line 10 is pulsed. If a 1 has been previously stored in the cell, point A is at voltage V(D). The line 10 pulse turns on T3 and current flows through T4, T3, and T10 to supply V(D). Point A therefore begins to go less positive turning off T1 and point B goes positive turning on T2 thus storing a 0 in the cell.

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