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Fast Three Input Adders

IP.com Disclosure Number: IPCOM000091657D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

The parallel adder produces the sum of three binary numbers of 24, 24, and 12 bits with a delay of only four basic logic circuit level units of delay from entry of input signals B, X, and D to points of egress of corresponding sum signals A. The inputs and outputs of the adder use only single-polarity signals. An adder of this type is useful for producing, in a single calculating cycle of very short duration, signals A representing an effective storage address. The signals B, D, and X, in such applications, represent respective base, displacement and index addressing quantities. The bits of these quantities and the corresponding sum bits are denoted in order of increasing significance by numerals 0...25.

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Fast Three Input Adders

The parallel adder produces the sum of three binary numbers of 24, 24, and 12 bits with a delay of only four basic logic circuit level units of delay from entry of input signals B, X, and D to points of egress of corresponding sum signals A. The inputs and outputs of the adder use only single-polarity signals. An adder of this type is useful for producing, in a single calculating cycle of very short duration, signals A representing an effective storage address. The signals B, D, and X, in such applications, represent respective base, displacement and index addressing quantities. The bits of these quantities and the corresponding sum bits are denoted in order of increasing significance by numerals 0...25. The adder is described first for the low-order 12 bits with 3 inputs per bit, drawing 1, and then for the high-order 12 bits with 2 inputs per bit, drawing 3.

To speed up formation of the sum, the low-order computation is performed in octal, 3-bit, groups. In the low-order first level of logic circuits, intergroup advance carries C2A, C5A, C8A, and C11A are generated when the high-order inputs of respective groups contain two or more binary signal conditions simultaneously. This amounts to an advance subtraction of eight units from the weighted sum of the respective group and a compensating addition of one unit, equal to octal eight, to the weighted total of the next higher order group. The diminished group then has a maximum weighted sum of thirteen or fourteen units, fourteen units in each octal group except the first due to the advance carry into each group but the first, from which only one additional carry C2, C5, C8, C11 need be generated to yield octal sum representations of appropriate form,
i.e., representing the numbers 0...7 uniquely. Other signals, produced in the low- order first level of logic circuit handling, include individual bit functions, related to the number of coincident binary 1 inputs present at each position, and intragroup advance carries C0, C1A, C3A, C4A, C6A, C7A, C9A, and C10A. The latter are similar in purpose to the intergroup advance carries. In the second bit position of each octal group except the first, the first level logic yields a second intragroup advance carry function C4B, C7B, C10B to the next higher order, third, bit position of the respective group. This second function denotes the presence of at least one binary 1 condition coincidentally in both the second and first place inputs of the group.

The second level of low-order logic circuit handling yields generate functions G, propagate functions P, and composite functions GP which include the conditions of the generate and propagate functions. Group functions are noted by slash marks, e.g., G6/8, GP9/11, etc. The least significant sum bit signal issues from this level, as well as the carries C1 and C2. The third low-order level produces half-sum functions H and carry functions C5, C8, C11, and C11. The next to le...