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Low Breakdown Voltage Memory Drive

IP.com Disclosure Number: IPCOM000091665D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Moore, RL: AUTHOR

Abstract

This memory drive circuitry prevents inductive kickback, from the driven memory line, from increasing the breakdown voltage requirements for the elements of the drive circuit.

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Low Breakdown Voltage Memory Drive

This memory drive circuitry prevents inductive kickback, from the driven memory line, from increasing the breakdown voltage requirements for the elements of the drive circuit.

In the quiescent state, transistors T1...T4 and the diodes D1...D7 are off while diodes D4, D10...D12 are conducting. The array is charged previously to voltage V by resistors R1 and R3. To read information scored in cores along line 10, T1 is first saturated by driving its base positive. When T1 conducts, its base is clamped through a saturated collector and diode T4 to V. Then T4 is turned on by driving its base positive. This completes the circuit from the positive terminal of current source I(hs) through T1, D1, line 10, D7 and T4. Rise time of the drive current depends upon the rate at which T4 is turned on, the magnitude of V and the drive line inductance and parasitic capacitances.

To end the drive pulse, T4 is turned off by driving its base negative. This causes the T4 end of the drive line to go positive so that that end of the drive line is clamped through D7 and D5 to V. The line inductance is then discharged through D5 and D7 to V thus preventing the voltage produced by turning off T4 from increasing the required breakdown voltage requirements of the transistors. After the line inductance is discharged, the drive line voltage at the D1 end of the line cuts off such diode and T1 to complete the read cycle. The write cycle proceeds in a similar m...