Browse Prior Art Database

Memory Cell

IP.com Disclosure Number: IPCOM000091675D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Berding, AR: AUTHOR

Abstract

A solid-state memory cell comprising a pair of cross-coupled transistors T10 and T12 includes diode inputs D14 and D16 and transistor output T18. D14 and D16 are biased so as to permit write time current flow only when T10 and T12 are switching. T18 is connected to the collector of T12 and yields a direct indication of the state of the cell. When information has been stored in the memory cell, D14 and D16 are reversed biased and, thus, nonconducting. A word line voltage applied at terminal 20 is held constant. One transistor, such as T10, is conducting and the other transistor, such as T12, is nonconducting. T18 is nonconducting.

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Memory Cell

A solid-state memory cell comprising a pair of cross-coupled transistors T10 and T12 includes diode inputs D14 and D16 and transistor output T18. D14 and D16 are biased so as to permit write time current flow only when T10 and T12 are switching. T18 is connected to the collector of T12 and yields a direct indication of the state of the cell. When information has been stored in the memory cell, D14 and D16 are reversed biased and, thus, nonconducting. A word line voltage applied at terminal 20 is held constant. One transistor, such as T10, is conducting and the other transistor, such as T12, is nonconducting. T18 is nonconducting.

In order to read information from the cell, the voltage applied to terminal 20 is increased. If the conduction of T10 represents the storage of a 1, and the conduction of T12 represents the storage of a 0, T18 then conducts if T10 is conducting. If T12 is conducting and T10 is off, T18 remains nonconducting. D14 and D16 are maintained reverse biased and, thus, no current flows through them.

In order to write information into the cell, the voltage applied to terminal 20 is once again increased. However, the voltage applied to terminal 22 or terminal 24 is correspondingly decreased. If it is desired to write a 1 into the cell, the voltage applied to terminal 22 is decreased. As D14 becomes forward-biased, the voltage applied to the base of T12 is pulled down, thus forcing T12 off and turning T10 on. The cell is symmetrical, so...