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Nand Nor Shift Register

IP.com Disclosure Number: IPCOM000091678D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Gurski, CS: AUTHOR

Abstract

The Nand-Nor shift register is a serial device utilizing four standard Nand or Nor circuits arranged into two serial latches per stage of delay. The device is specifically for integrated circuit implementation, since control of the characteristics required for operation of the device can only be achieved in an integrated circuit environment, in which the delay can be expected to track between circuits on the same chip.

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Nand Nor Shift Register

The Nand-Nor shift register is a serial device utilizing four standard Nand or Nor circuits arranged into two serial latches per stage of delay. The device is specifically for integrated circuit implementation, since control of the characteristics required for operation of the device can only be achieved in an integrated circuit environment, in which the delay can be expected to track between circuits on the same chip.

A Nand, And-Invert, implementation of a three-stage shift register using this method is shown at A. Waveforms of the operation with an assumed Data input are shown at B. Tolerable variation in the timing relation of Data to the phases 1 and 2 and its effect upon successive stages is indicated by dotted lines in drawing B. Each Nand includes a transistor which is switched to its on state to produce a negative output level only when both inputs are positive. All other input combinations turn the transistor off to produce a positive output level. Trigger AA develops phase 1 and phase 2 pulses which are essentially complementary signals. These phase pulses control shifting of the register, the shift rate being equal to their frequency.

Assume the input of Data is synchronized with phase 2 as indicated at B. Coincidence of positive levels of the Data and phase 2 signals at the input of Nand BA causes its output to go negative, in turn changing the output of Nand AB to positive. The subsequent transition of phase 1 to the positive level changes the output of Nand BB to a negative level, latching up the AB, BB combination. However, for this latchup to occur, it is necessary that BB turn on, that is, its output goes negative, and latch back through AB, maintaining the output of AB positive, before the output of BA goes negative due to phase 2 going negative.

At the completion of the latchup of the AB, BB combination, the negative output from BB applied to Nand AC causes its output level to go positive. This positive-going pulse, combined with the next positive going pulse from phase 2, turns Nand BC on. The negative-going output of BC is applied to AC latching up the AC, BC combination. This same negative level, applied to Nand AD, causes a positive level to be applied to BD. The combination of the positive level of AD with the next positive-going level of phase 1 turns Nand BD on to provide a negative level to AD to latch up the AD, BD combination and to AE...